The present invention relates to testing electrical circuits.
In the field of testing printed circuit boards, for example such boards before they have components added, it is known to test for open or short circuit faults in conductive tracks by making resistance value checks or capacitance value checks. Such checks may be made using at least one electrical testing probe, automatically controlled by a computer system to contact the board at appropriate points to make appropriate measurements.
Printed circuit boards may comprise a very large number of conductive tracks, forming a large number of networks, and it is necessary to know if there are undesired short circuits between such networks. For a printed circuit board having N such networks, the number of resistance based measurements required to verify that no undesired short circuit electrical paths exist between any two networks is: EQU N (N-1)/2
This is explained as follows. First, the resistance between a first network and every other network is measured, meaning a first number (N - 1) of measurements. Then, the resistance between a second network and every other network (except the first) is measured, meaning a second number ((N - 1) - 1) of measurements. Then, the resistance between a third network and every other network (except the first and second) is measured, meaning a third number ((N - 1)- 2) of measurements, and so on until the Nth network. The total number of measurements as a result of this is a series represented as above.
For a printed circuit board with a thousand networks, making resistance measurements between all networks as above would mean substantially half a million measurements and if, as is typical, the measurements are made using electrical testing probes, this would result in an extremely long test duration. A means of reducing the number of measurements in testing for short circuits between networks would clearly be an advantage.
To reduce the number of probe movements, U.S. Pat. No. 4,565,966 (Burr, et al) discloses a method and apparatus for testing a circuit board using a combination of capacitance measurements, between networks and a reference, and end-to-end resistance measurements of networks, the measured capacitance and resistance values being compared with respective pre-established values (obtained in a learning mode) for a board with no faults. There is also disclosed in Burr, et al a diagnostic routine for those networks which have been identified as being possibly faulty. More particularly, for those of the networks which have been identified as being possibly faulty and which have the same capacitance value in relation to the reference, inter-network resistance checks are carried out to check if any of them are short-circuited together, on the rationale that networks which have the same capacitance value in relation to the reference are likely to be short-circuited together. It would be possible to use such a routine for all the networks of a printed circuit board, by measuring the capacitance between each one of the networks and a reference, and carrying out tests for short circuits between pairs of networks which have the same capacitance value. However, this might result in too many short circuit tests being carried out than are actually necessary, since it is possible that two networks have the same capacitance value coincidentally and might not be actually short-circuited together.